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VHDL Sorting Algorithm for FPGA

VHDL Sorting Algorithm for FPGA

Using VHDL

Implement and test a sort algorithm(QuickSort, Merge sort e.t.c- pick any) on FPGA boards(Basys3 Board)
Unsorted data are stored in Block RAMs.
Initialization of the Block RAMs should be done through an external file.
After the sorting is finished, the sorted data are displayed in a terminal on the host system through a UART transmitter


Specific Requirements

Data inputs are unsigned and 16-bit wide.

Data inputs are defined in hexadecimal format in an external file to initialize the block RAM.

The minimal size of data inputs should be >= 16.

The sorted results displayed on the terminal through UART are also in hexadecimal format.

Your design should support the selection of sorting in an either increasing or decreasing order.


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