Questions

1. Which of the following statements is true? (correct: 2 marks, incorrect: -1 mark, don’t know: 0 marks)
   i. Unconditional outputs are dependent on the present state and next state
   ii. Unconditional outputs are dependent on the inputs, present state and next state
   iii. Conditional outputs are only dependent on the present state
   iv. Unconditional outputs are dependent on the inputs and next state
   v. Conditional outputs are only dependent on the next state
   vi. Unconditional outputs are only dependent on the inputs
   vii. Conditional outputs are dependent on the inputs and present state
   viii. Conditional outputs are dependent on the inputs and next state
   ix. Unconditional outputs are only dependent on the next state
   x. I don’t know
2. You wish to design a counter which counts through the sequence {Q1,Q0} = {0,0}; {0,1}; {1,0}; and
   then repeats. Use the ASM design process to obtain Boolean equations for Q1n and Q0n. Which of
   the following implement the required counter? (correct: 4 marks, incorrect: -2 marks, don’t know: 0
   marks)
   i. ?0? = ?0 , ?1? = ?̅̅̅1̅ ?̅̅̅0̅
   ii. ?0? = ?̅̅̅1̅ ?̅̅̅0̅ , ?1? = ?0
   iii. ?0? = ?̅̅̅0̅ , ?1? = ?1 ⨁ ?0
   iv. ?0? = ?̅̅̅1̅ , ?1? = ?1 ⨁ ?0
   v. None of the above
   vi. I don’t know
   ELEC1202 Problem Sheet 4 Page 2 of 4
3. Consider the ASM chart shown in Fig 1. Which of the following statements is correct?
   (correct: 2 marks, incorrect: -1 mark, don’t know: 0 marks)
   i. It represents a Mealy machine, and will require 1 D-type flip-flop to implement
   ii. It represents a Mealy machine, and will require 3 D-type flip-flops to implement
   iii. It represents a Mealy machine, and will require 6 D-type flip-flops to implement
   iv. It represents a Moore machine, and will require 1 D-type flip-flop to implement
   v. It represents a Moore machine, and will require 3 D-type flip-flops to implement
   vi. It represents a Moore machine, and will require 6 D-type flip-flops to implement
   vii. I don’t know
   Fig 1
4. Consider the Boolean equation shown below, which were created using the ASM design process.
   Which of the following statements is correct?
   (correct: 2 marks, incorrect: -1 mark, don’t know: 0 marks)
   ?0? = ?̅?̅ + ?̅?1 ?̅̅̅0̅ , ?1? = ? ?̅̅̅1̅ ?0 + ? ? ?1 ?̅̅̅0̅ , ? = ? ?̅ ?̅̅̅1̅ ?0
   i. There is 1 input and 2 outputs, and the circuit will require 1 D-type flip-flop to implement
   ii. There is 1 input and 2 outputs, and the circuit will require 2 D-type flip-flops to implement
   iii. There is 1 input and 2 outputs, and the circuit will require 3 D-type flip-flops to implement
   iv. There are 2 inputs and 1 output, and the circuit will require 1 D-type flip-flop to implement
   v. There are 2 inputs and 1 output, and the circuit will require 2 D-type flip-flops to implement
   vi. There are 2 inputs and 1 output, and the circuit will require 3 D-type flip-flops to implement
   vii. I don’t know
   NONE
   N 0
   1 LIGHTS GOTO_ONE
   X | N 1
   0 ONE
   N 0
   1 LIGHTS GOTO_TWO
   N 1
   0 TWO
   X 1 0
   X 0
   1 LIGHTS GOTO_ZERO
   X 1 0
   ELEC1202 Problem Sheet 4 Page 3 of 4
5. Consider the ASM chart and timing diagram shown in Fig 2. The traces for M and N have deliberately
   left blank, for you to complete. Assume that, at t=0, the system is in state ‘zero’. What logic level are
   A and B? (correct: 4 marks, incorrect: -2 marks, don’t know: 0 marks)
   Fig 2
   i. A = 0, B = 0
   ii. A = 0, B = 1
   iii. A = 1, B = 0
   iv. A = 1, B = 1
   v. A = X, B = X
   vi. I don’t know
6. You wish to design a 2-bit up-down counter with one input M. When M=0, the counter counts up (i.e.
   it follows the sequence {Q1,Q0} = {0,0} → {0,1} → {1,0} → {1,1}; and then repeats). When M=1, the
   counter counts down (i.e. it follows the sequence {Q1,Q0} = {1,1} → {1,0} → {0,1} → {0,0}; and then
   repeats). Use the ASM design process to obtain Boolean equations for Q1n and Q0n. Which of the
   following implement the required counter?
   (correct: 6 marks, incorrect: -3 marks, don’t know: 0 marks)
   i. ?0? = ?̅̅̅0̅ , ?1? = ?̅̅̅1̅ ?̅̅̅0̅ ? + ?̅̅̅1̅ ?0 ?̅ + ?1 ?0 ? + ?1 ?̅̅̅0̅ ?̅
   ii. ?0? = ?̅ ?̅̅̅1̅ + ? ?1 , ?1? = ?̅ ?0 + ? ?̅̅̅0̅
   iii. ?0? = ?̅̅̅0̅ , ?1? = ?̅̅̅1̅ ?̅̅̅0̅ ?̅ + ?1 ?0 ?
   iv. ?0? = ?0 ? + ?1 ?̅̅̅0̅ + ?1 ? , ?1? = ?̅̅̅0̅
   v. ?0? = ?̅̅̅0̅ ?̅ + ? ?1 , ?1? = ?̅ ?1 + ? ?̅̅̅0̅
   vi. ?0? = ?̅̅̅0̅ ?̅ + ? ?0 , ?1? = ?̅ ?1 + ? ?̅̅̅1̅
   vii. None of the above
   viii. I don’t know
   ELEC1202 Problem Sheet 4 Page 4 of 4
7. Which of the following statements is correct?
   (correct: 2 marks, incorrect: -1 mark, don’t know: 0 marks)
   i. A divide-by-four counter counts from 0 to 15
   ii. A divide-by-five counter counts from 0 to 5
   iii. A divide-by-six counter counts from 0 to 64
   iv. A divide-by-seven counter counts from 0 to 6
   v. A divide-by-eight counter inputs one byte of data (e.g. 01010002) and outputs the numerical
   value of number divided by 8 (e.g. 000010102)
   vi. I don’t know
8. A digital circuit is required that can detect the 2-bit binary sequence: 00, [11], 10, 01; where [11]
   means a sequence of one or more 11’s (note, the most significant bit is the one on the left). For
   example, the following are all valid bit sequences:
   00, 11, 10, 01
   00, 11, 11, 10, 01
   00, 11, 11, 11, 10, 01
   00, 11, 11, 11, 11, 11, 10, 01
   00, 11, 11, 11, 11, 11, 11, 10, 01
   … etc
   The binary sequence is inputted to your system via the inputs A (least significant bit) and B (most
   significant bit). Assume that the binary sequence is clocked using the same clock as your circuit. The
   output L should be asserted for one clock cycle every time that the sequence is detected. Use the
   ASM design process to obtain Boolean equations. Which of the following equations correctly
   implement the specification? Note – if you get stuck you may wish to try and ‘reverse engineer’ the
   ASM from the equations.
   (correct: 10 marks, incorrect: -5 marks, don’t know: 0 marks)
   i. ?0? = ? ?̅ + ?̅?1 ?̅̅̅0̅ , ?1? = ? ? ?̅̅̅1̅ ?0 + ? ?1 ?̅̅̅0̅ , ? = ?̅?̅ ?1 ?0
   ii. ?0? = ?̅?̅ + ?̅?1 ?̅̅̅0̅ , ?1? = ? ? ?̅̅̅1̅ ?0 + ? ?1 ?̅̅̅0̅ , ? = ? ?̅ ?1 ?0
   iii. ?0? = ?̅?̅ + ?̅?1 ?̅̅̅0̅ , ?1? = ? ?̅̅̅1̅ ?0 + ? ? ?1 ?̅̅̅0̅ , ? = ? ?̅ ?̅̅̅1̅ ?0
   iv. ?0? = ? ?̅ + ?̅? ?1 ?̅̅̅0̅ , ?1? = ? ? ?̅̅̅1̅ ?0 + ? ?1 ?̅̅̅0̅ , ? = ? ?̅ ?̅̅̅1̅ ?0

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