## Genetically Modified Food Labeling

This assignment is assessed and worth 15% of your mark for EG-143. See the end for full instructions.**Part A: Design brief to circuit**

Q1. In a competition there are four judges: the Supreme Judge (SJ), the Assistant Judge (AJ) and the Ordinary Judges

(OJ1 and OJ2). If the Supreme Judge and any other judge rule that the competitor has won, then the competitor

is successful. If the Assistant Judge and both Ordinary Judges rule that the competitor has won, then the

competitor is successful.

(i) Draw the Karnaugh map representing this situation, where the output is ‘1’ when the competitor is

successful and ‘0’ if not and use the K-map to derive the simplified logic expression for when a competitor

will be successful.

(ii) By re-arranging the expression, what is the minimum number of 2- and 3-input logic gates it can be realised

with? Design this circuit in Multisim, show your design and generate the truth table.

[4 marks]**Part B: Logic circuit design**

Q2. (i) Design a 2-input 1-output multiplexer, inside a hierarchical block. Explain your design. Name your block with

your student number: eg “123456 multiplexer”.

(ii) Test your circuit in block form, showing the truth table from Multisim. [4 marks]

Q3. (i) Design an 8-bit ripple adder which can add together two 8-bit numbers, inside a hierarchical block. Explain

your design. Name your block with your student number: eg “123456 ripple adder”.

(ii) Test your circuit in block form, showing four example additions with manual calculations to show they are

correct. [4 marks]

Q4. (i) Design a 7-segment LED driver using the truth table given in the lecture notes, inside a hierarchical block.

Assume only numbers from 0 to 9 will be sent to your block. Explain your design. Name your block with your

student number: eg “123456 LED driver”.

(ii) Test your circuit in block form using digital interactive constants to represent the inputs, and showing for

every input combination what the LED display shows. Explain your testing. [4 marks]

**Part C: Cascading your own blocks to create new circuits**

Q5. (i) Construct a circuit which can take an 8-bit signed integer (2’s compliment) as an input and convert that

number in to the equivalent 8-bit unsigned integer, with an extra negative flag which is positive if the number is

negative and zero if not. You should do this by re-using your own blocks for the multiplexer and adder. Don’t despair if you can’t immediately see how to do this – it will take some thought. First see on paper whether you

can find a way to achieve the required conversion by following the process given in the lecture notes. There are other ways to achieve this conversion so partial marks will be given if you fully explain an alternative approach.

(ii) Test this circuit by using digital interactive constants as the inputs and digital probes on the outputs. For four test input signals manually calculate what the output should be, and then test your circuit showing screen shots

of what your circuit shows:

• 0000 0000

• 1111 1111

• Take the second and third digits of your student number as a pair, use the negative of that number in 8- bit 2’s compliment. For example if your student number is 123456 take 23, make it negative −23, and in

2’s compliment (−23)10 is (1110 1001)2 → use this as a test signal

• Take the fourth and fifth digits of your student number as a pair, use the negative of that number in 8-bit 2’s compliment. For example if your student number is 123456 take 45, make it negative −45, and in 2’s

compliment (−45)10 is (1101 0011)2 → use this as a test signal

[8 marks]

Q6. Building on your circuit from Q5:

(i) Connect up your 7-segment display driver from Q4 to the four least significant output bits of the converter in

Q5, and connect the output of your display driver to a seven segment LED display. In front of the seven segment

LED display add another identical one. For this preceding display set every segment off permanently, except for

segment g which should be connected to the is_negative flag from Q5. For three test input signals manually

calculate what the output display should show, and then test your circuit showing screen shots of what your

circuit and displays show:

• 0000 0000

• Take the fourth digit of your student number, use the negative of that number in 8-bit 2’s compliment.

For example if your student number is 123456 take 4, make it negative −4, and in 2’s compliment (−4)10

is (1111 1100)2 → use this as a test signal

• Take the sixth digit of your student number, use the negative of that number in 8-bit 2’s compliment.

For example if your student number is 123456 take 6, make it negative −6, and in 2’s compliment (−6)10

is (1111 1010)2 → use this as a test signal

[4 marks]

Correct PDF submission, student number as filename, with cover page and clear presentation: [2 marks]**Instructions**

There is lots of circuit design in this assignment with freedom for you to customise how you lay out and solve the

problems. Therefore marks are awarded not just for whether your design works, but whether it is clear and easy to

understand and whether you have explained your reasoning and method clearly.

You must submit ONE pdf file, with the filename your student number (eg 123456.pdf) which contains all your

solutions with the engineering cover sheet as the first page, using the link on the Blackboard page for EG-143 2018

Logic Assignment 2. The deadline is: Friday 7th December 2018 at 5pm.

This work is assessed and worth 15% of your mark for EG-143. Therefore you must work alone, and submit your completed work by the deadline or you will score zero. The College will not accept IT issues so submit well ahead of time. Emailed submissions will not be accepted.

If you have any questions please check the online FAQ at: http://bit.ly/2fsY0jX or ask in the lab sessions.

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