## design and test a three-digit binary-coded-decimal (BCD) adder capable of adding positive and negative BCD numbers

1. Introduction

For this assignment you will design and test a three-digit binary-coded-decimal

(BCD) adder capable of adding positive and negative BCD numbers. The assignment

has a combinational part and a sequential part. You will implement it in two phases;

first the combinational part and next the sequential part.

1.1 Assignment Behavioral Specification

• The BCD adder you design must be capable of adding two three-digit BCD

operands to produce a three-digit sum. Each of the two operands can be either

positive or negative, so the adder must, in effect, be capable of both addition and

subtraction.

• You will represent the operands and sum using 13-bit binary vectors where 12

of the bits are the three 4-bit BCD digits and the 13th bit is a sign bit (0 if the

number is positive and 1 if it is negative). This is essentially a sign-plusmagnitude

representation where the magnitude is represented with the BCD

code.

• The adder should also have a one-bit overflow output signal that is 1 if the

addition results in an overflow (a magnitude that is too big to be represented

with 3 BCD digits) and 0 otherwise. BCD codes and arithmetic are discussed in the

textbook.

1.2 Assignment Organization

The adder is to be organized as three identical digit-adders connected in a ripplecarry

configuration. Each of the digit-adders will be capable of adding two 4-bit BCD

digits and a 1-bit carry/borrow input to produce a 4-bit BCD sum and 1-bit

carry/borrow output. The adder should implement the following general algorithm:

1. The adder checks the signs and relative magnitude of the two operands.

2. If signs are the same, the adder adds the operands and makes the sign of the

result equal the signs of the operands.

3. If the signs differ, then the adder compares the magnitudes of the operands,

subtracts the smaller from the larger, and sets the sign of the result equal to

the sign of the larger. Note that if the result is 0, the sign of the result must be

positive (0 sign bit).

A high-level block diagram for the assignment is given in Figure 1. It shows the main

data flow paths that connect the modules, but does not show the signals that

connect to the control unit. That module will need inputs from the other modules

and will generate control signals for all the modules. Part of the assignment

assignment is to figure out what these control signals should be. The remainder of

this section describes the behavior of the modules in this diagram.

DIGITADD

This is a digit adder that takes two 4-bit BCD digits and a carry/borrow input and

produces a 4-bit BCD sum or difference and a carry/borrow output.

REGUNIT

This module contains two 4-bit registers that hold the input operands for the

DIGITADD module. The BCD input digits must be entered sequentially, one at a time,

into the REGUNIT registers. This unit is also responsible for swapping the operands

when necessary because the available adders can only subtract the B input from the

A input, not the other way around. It is also convenient to add logic to the REGUNIT

to determine which of the input operands is larger (needed to determine if the

operands must be switched). The logic for this should be designed so that when

several REGUNIT modules are connected in series, they will determine which of the

3-digit BCD numbers is larger (or whether they are equal).

CTRLUNIT

This module takes information from the other modules and generates the control

signals for those modules. It must check the signs and magnitudes of the operands

and decide whether to do an addition or subtraction and whether to swap the

operands. It is also responsible for computing the sign of the result.

2. Assignment Implementation

This section gives some more detailed information about how to implement the

modules in the block diagram above. Each of the modules should be implemented as

a VHDL module. We will start with the combinational part of the implementation to

be denoted as Phase I. This implementation will be submitted first.

2.1 PHASE I

A. DIGITADD

Probably the best way to implement the digit adder is by first doing a binary

addition/subtraction and then correcting the sum, if it is outside the range of valid

BCD digits (i.e., greater than 9). The correction can be implemented by adding a

correction value to the intermediate result produced by the first addition or

subtraction. You can implement this with a 4-bit binary adder/subtractor to do the

first addition/subtraction and another binary adder to perform the correction. You

must determine when to do the corrections and what correction values to add. You

will need logic to generate the correction value.

Next, you combine three copies of the digit adder using a structural VHDL module

that uses the other modules as components.

B. Design and Implementation

In this phase, you will develop an algorithm for BCD addition and subtraction and

write a behavioral VHDL module to implement this algorithm. Test the algorithm for

correctness by simulating the VHDL module. You should use high-level VHDL

operations rather than binary logical operations or gate instantiations. For example,

use processes, conditional operations (IF, CASE, etc.), and comments to make it

easy for the reader to understand your algorithm.

C. Testing

It is frequently impractical to test a large circuit by applying all possible input

values. Therefore, it is necessary to select a small subset of test signals that are likely

to catch most of the possible errors. Part of this assignment is to decide how to test

it (i.e., which test inputs to use).

While there is very little theory to help you select test inputs, there are some

guidelines you should consider. For example:

1. Break the assignment into smaller parts and test them exhaustively. For

example, an obvious approach is to test the digit-adder by itself to make sure

it is working before using it in the full adder. (0+0; 0+1; 2+3; 4+5; 5+6; 9+9)

2. Find test signals for the full adder that generate carry signals between stages

and check all the extreme cases and any special cases.

(000+000; 000+001; 123+345; 234+567; 789+777; 999+999)

(000+(-000)); 000+(-001); 345+(-123); 567+(-234); 777+(-789); 999+(-999))

D. Deliverables

Upload to Moodle your (.vhd) files only of all the components that you designed in

addition to the testbench file only for the overall adder. This testbench file will have

the test cases that you selected.

2.2 PHASE II

A. REGUNIT

You should implement the registers in this module so that when the three REGUNIT

modules are connected together, the three A-operand registers form a shift register

and the three B-operand registers form another shift register. These shift registers

should shift from the least significant digit to the most significant digit.

Your input will be loaded to these shift registers, 4 bits at a time at the least

significant part and then shifted to the most significant part. You input the most

significant digit of A and you shift by 4 bits, then you input the most significant digit

of B and you shift by 4 bits, and so on.

You can use multiplexers on the outputs of the registers to swap the two operands.

The logic that checks the relative magnitudes of the operands should take

information from the comparison logic in the previous REGUNIT module and

produce output signals that represent the result of comparing all digits through this

position. These output signals are then passed to the next REGUNIT module. The

output signals of the comparison logic in the last REGUNIT module indicate which of

the full 3-digit operands is largest (or whether or not they are equal).

B. CTLUNIT

This module must contain two flip-flops to hold the signs of the two operands. The

module must also contain logic to use the signs of the two operands and the result of

the magnitude comparison of the operands to compute the sign of the result and to

tell the DIGITADD modules whether to add or subtract.

C. Testing

Repeat the following tests that you performed in Phase I:

• 234 + 567

• 567 + (-234)

• 777 + (-789)

D. Deliverables

Upload to Moodle your (.vhd) files only of all the components that you designed in

addition to the testbench file only for the overall adder. This testbench file will have

the above test cases.

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